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ka i - 10100 image sensor 3648 (h) x 2760 (v) interline ccd im age sensor j u ne 4 , 201 4 device performance s pecification revision 1. 1 ps - 0027
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 2 table of contents summary specification ................................ ................................ ................................ ................................ ................................ ......................... 5 description ................................ ................................ ................................ ................................ ................................ ................................ .... 5 features ................................ ................................ ................................ ................................ ................................ ................................ ......... 5 applications ................................ ................................ ................................ ................................ ................................ ................................ .. 5 ordering information ................................ ................................ ................................ ................................ ................................ ............................ 6 device description ................................ ................................ ................................ ................................ ................................ ................................ . 7 architectu re ................................ ................................ ................................ ................................ ................................ ................................ .. 7 pixel ................................ ................................ ................................ ................................ ................................ ................................ ............ 8 vertical to horizontal transfer ................................ ................................ ................................ ................................ ............................ 8 horizontal register to floating diffusion ................................ ................................ ................................ ................................ ......... 8 horizontal register ................................ ................................ ................................ ................................ ................................ ..................... 9 output structure ................................ ................................ ................................ ................................ ................................ ..................... 9 recommended circuits ................................ ................................ ................................ ................................ ................................ ........... 10 output gate bypass ................................ ................................ ................................ ................................ ................................ ............. 10 output load ................................ ................................ ................................ ................................ ................................ ........................... 10 physical descrip tion ................................ ................................ ................................ ................................ ................................ ................. 11 pin description and device orientation ................................ ................................ ................................ ................................ ......... 11 imaging performance ................................ ................................ ................................ ................................ ................................ .......................... 12 typical operational conditions ................................ ................................ ................................ ................................ ............................. 12 specifications ................................ ................................ ................................ ................................ ................................ ............................. 12 typical performance curves ................................ ................................ ................................ ................................ ................................ ............ 14 defect definitions ................................ ................................ ................................ ................................ ................................ ................................ 16 operational conditions ................................ ................................ ................................ ................................ ................................ ........... 16 specif ications ................................ ................................ ................................ ................................ ................................ ............................. 16 test definitions ................................ ................................ ................................ ................................ ................................ ................................ ..... 17 test regions of interest ................................ ................................ ................................ ................................ ................................ ......... 17 overclocking ................................ ................................ ................................ ................................ ................................ ............................. 17 tests ................................ ................................ ................................ ................................ ................................ ................................ ............. 18 dark field defect test ................................ ................................ ................................ ................................ ................................ .......... 18 bright field defect test ................................ ................................ ................................ ................................ ................................ ....... 18 operation ................................ ................................ ................................ ................................ ................................ ................................ .................. 19 absolute maximum ratings ................................ ................................ ................................ ................................ ................................ ... 19 powe r - up sequence ................................ ................................ ................................ ................................ ................................ ................. 20 alternate power up sequence ................................ ................................ ................................ ................................ .............................. 20 dc bias operating conditions ................................ ................................ ................................ ................................ ............................... 21 supplied voltage levels ................................ ................................ ................................ ................................ ................................ ......... 21 ac operating conditions ................................ ................................ ................................ ................................ ................................ ........ 22 clock levels ................................ ................................ ................................ ................................ ................................ ........................... 22 clock capacitance ................................ ................................ ................................ ................................ ................................ ................ 22 timing ................................ ................................ ................................ ................................ ................................ ................................ ......................... 23 requirements and chara cteristics ................................ ................................ ................................ ................................ ....................... 23 timing modes ................................ ................................ ................................ ................................ ................................ ................................ .......... 24 full resolution interlaced readout (fa mode) ................................ ................................ ................................ ................................ . 25 flow chart fa ................................ ................................ ................................ ................................ ................................ ........................ 25 fa mode pixel order ................................ ................................ ................................ ................................ ................................ ........... 26 fa frame rat e ................................ ................................ ................................ ................................ ................................ ....................... 27 fa clocking overview ................................ ................................ ................................ ................................ ................................ .......... 28 progressive scan 1x2 binning readout (fb2 mode) ................................ ................................ ................................ ........................ 30
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 3 flow chart fb2 ................................ ................................ ................................ ................................ ................................ ...................... 30 progressive scan 2x2 binning readout (fb4 mode) ................................ ................................ ................................ ........................ 31 flow chart fb4 ................................ ................................ ................................ ................................ ................................ ...................... 31 progressive scan 4x4 binning readout (fd16 mode) ................................ ................................ ................................ ..................... 32 flow chart fd16 ................................ ................................ ................................ ................................ ................................ ................... 32 vertical tim ing sequence ................................ ................................ ................................ ................................ ................................ .................. 34 fa mode ................................ ................................ ................................ ................................ ................................ ................................ ...... 34 sequence va ................................ ................................ ................................ ................................ ................................ .......................... 34 sequence vb ................................ ................................ ................................ ................................ ................................ .......................... 35 sequence vc ................................ ................................ ................................ ................................ ................................ .......................... 36 sequence vd ................................ ................................ ................................ ................................ ................................ .......................... 37 sequence ve ................................ ................................ ................................ ................................ ................................ .......................... 38 fb2 and fb4 mode ................................ ................................ ................................ ................................ ................................ ................... 39 sequence vf ................................ ................................ ................................ ................................ ................................ .......................... 39 sequence vg ................................ ................................ ................................ ................................ ................................ .......................... 40 sequence vn ................................ ................................ ................................ ................................ ................................ ......................... 41 fd16 mode ................................ ................................ ................................ ................................ ................................ ................................ . 42 sequence vh ................................ ................................ ................................ ................................ ................................ .......................... 42 sequence vi ................................ ................................ ................................ ................................ ................................ ........................... 43 electronic shuttering ................................ ................................ ................................ ................................ ................................ ............... 44 storage and handling ................................ ................................ ................................ ................................ ................................ .......................... 45 storage conditions ................................ ................................ ................................ ................................ ................................ ................... 45 esd ................................ ................................ ................................ ................................ ................................ ................................ ............... 45 cover glass care and cleanliness ................................ ................................ ................................ ................................ ......................... 45 environmental exposure ................................ ................................ ................................ ................................ ................................ ........ 45 soldering recommendations ................................ ................................ ................................ ................................ ................................ 45 mechanical drawings ................................ ................................ ................................ ................................ ................................ ........................... 46 complete d assembly ................................ ................................ ................................ ................................ ................................ ............... 46 cover glass ................................ ................................ ................................ ................................ ................................ ................................ . 48 quality assurance and reliability ................................ ................................ ................................ ................................ ................................ .. 50 quality and reliability ................................ ................................ ................................ ................................ ................................ ............. 50 replacement ................................ ................................ ................................ ................................ ................................ .............................. 50 liability of the supplier ................................ ................................ ................................ ................................ ................................ ........... 50 liability of the customer ................................ ................................ ................................ ................................ ................................ ........ 50 te st data retention ................................ ................................ ................................ ................................ ................................ ................. 50 mechanical ................................ ................................ ................................ ................................ ................................ ................................ .. 50 life support applications policy ................................ ................................ ................................ ................................ ................................ .... 50 revision changes ................................ ................................ ................................ ................................ ................................ ................................ ... 51 mtd/ps - 1029 ................................ ................................ ................................ ................................ ................................ ............................. 51 ps - 0027 ................................ ................................ ................................ ................................ ................................ ................................ ....... 51
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 4 table of figures figure 1: block diagram ................................ ................................ ................................ ................................ ................................ ............... 7 figure 2: output architecture (each output) ................................ ................................ ................................ ................................ .......... 9 figure 4: recommended output structure load diagram. ................................ ................................ ................................ .............. 10 figure 5: pinout diagram ................................ ................................ ................................ ................................ ................................ ........... 11 figure 6: typical spectral response C clear cover glass ................................ ................................ ................................ .................... 14 figure 7: typical angular response C clear cover glass ................................ ................................ ................................ .................... 14 figure 8: power vs. clock rate ................................ ................................ ................................ ................................ ................................ .. 15 figure 9: overclock regions of interest ................................ ................................ ................................ ................................ ................. 17 figure 10: power - up sequence diagram ................................ ................................ ................................ ................................ ................ 20 figure 11: diagram of vertical clock overshoot to be avoided ................................ ................................ ................................ ......... 20 figure 12: frame rates ................................ ................................ ................................ ................................ ................................ ............... 2 4 figure 13: fa mode - timing flow ................................ ................................ ................................ ................................ ............................ 25 figure 14: fa mode C pixel order diagram ................................ ................................ ................................ ................................ ............ 26 figure 15: fa timing overview ................................ ................................ ................................ ................................ ................................ . 28 figure 16: fa integration timing overview ................................ ................................ ................................ ................................ .......... 29 figure 17: fb2 mode - timing flow ................................ ................................ ................................ ................................ .......................... 30 figure 18: fb4 mode - timing flow ................................ ................................ ................................ ................................ .......................... 31 figure 19: fd16 mode - timing flow ................................ ................................ ................................ ................................ ....................... 32 figure 20: fd16 mode C clock order information ................................ ................................ ................................ ............................... 33 figure 21: fa mode C vertical timing sequence - va ................................ ................................ ................................ .......................... 34 figure 22: fa mode C vertical timing sequence - vb ................................ ................................ ................................ .......................... 35 figure 23: fa mode C vertical timing sequence - vc ................................ ................................ ................................ .......................... 36 figure 24: fa mode C vertical timing sequence - vd ................................ ................................ ................................ .......................... 37 figure 25: fa mode C vertical timing sequence - ve ................................ ................................ ................................ .......................... 38 figure 26: fb2/fb4 mode C vertical timing sequence - vf ................................ ................................ ................................ ............... 39 figure 27: fb2/fb4 mode C vertical timing sequen ce - vg ................................ ................................ ................................ ............... 40 figure 28: fb2/fb4 mode C vertical timing sequence - vn ................................ ................................ ................................ ............... 41 figure 29: fd16 mode C vertical timing sequence - vh ................................ ................................ ................................ ..................... 42 figure 30: fd16 mode C vertical timing sequence - vi ................................ ................................ ................................ ....................... 43 figure 31: completed assembly (1 of 2) ................................ ................................ ................................ ................................ ................ 46 figure 32: completed assembly (2 of 2) ................................ ................................ ................................ ................................ ................ 47 figure 33: glass drawing ................................ ................................ ................................ ................................ ................................ ............ 48 figure 34: glass transmission ................................ ................................ ................................ ................................ ................................ ... 49
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 5 summary specification kai - 10100 i mage sensor d escription the kai - 10100 image sensor is a 10 million pixel, 22.5mm diagonal (four thirds format) high performance color interline transfer ccd image sensor. advanced 4.75 micron square pixels provide outstanding sensitivity and dynamic range, and overflow protection is provided in each pixel through the use of a vertical overflow drain. the sensor employs a 4 - field interlac ed design for full resolution readout, or can be read as a progressive scan device using 1x2, 2x2, or 4x4 color binning modes. use of these color binning modes provides significantly improved sensitivity and faster readout rates, making this sensor ideal for both scientific and photographic applications. f eatures ? high resolution with low noise ? high sensitivity and dynamic range ? on - sensor color binning for enhanced sensitivity and frame rate ? electronic shutter a pplications ? intelligent transportation systems ? photography ? scientific parameter typical value architecture interline ccd; interlaced or progressive scan total number of pixels 3868 (h) x 2892 (v) = 11.1 m number of effective pixels 3776 (h) x 2856 (v) = 10.8 m number of active pixels 3760 (h) x 2840 (v) = 10.7 m pixel size 4.75 m (h) x 4.75 m (v) active image size 17.86 mm (h) x 13.49 mm (v) 22.5 mm (diagonal) aspect ratio 4:3 number of outputs 2 output sensitivity 32 v/e saturation signal 25,000 electrons quantum efficiency r (630 nm), g (550 nm), b (470 nm) 32%, 42%, 40% total noise 10 electrons dark current (t= 40 c) 0.06 na/cm 2 dark current doubling temperature 7.5 c dynamic range 64 db charge transfer efficiency > 0.99999 blooming suppression > 100x image lag 5 e - maximum data rate 30 mhz frame rate full resolution (fa mode) 1x2 bin (3760 x 1420) (fb2 mode) 2x2 bin (1880 x 1420) (fb4 mode) 4x4 bin (940 x 710) (fd16 mode) 5 fps 10 fps 10 fps 19 fps package 32 - pin, cerdip, 0.070 pin spacing cover glass clear all parameters above are specified at t = 20 c, unless otherwise noted
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 6 ordering information catalog number product name description marking code 4h2106 kai - 10100 - cxc - cb - xa color (bayer rgb), special microlens , cerdip package sidebrazed pins, clear cover glass (no coatings), standard grade kai - 10100 - cxc (lot number) 4h2107 kai - 10100 - cxc - cb - xe color (bayer rgb), special microlens, cerdip package sidebrazed pins, clear cover glass (no coatings), engineering grade see application note product naming convention for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, pleas e visit our w eb site at www.truesenseimaging.com . please address all inquiries and purchase orders to: truesense imaging, inc. 1964 lake avenue rochester, new york 14615 phone: (585) 784 - 5500 e - mail: info@truesenseimaging.com on semiconductor reserves the right to change any information contained herein without notice. all information furnished by on semiconductor is believed to be accurate.
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 7 device description a rchitecture figure 1 : block diagram surrounding the periphery of the device is a border of light shielded pixels creating a dark region. within this dark region are light shielded pixels that include 74 trailing dark pixels on every line. there are also 20 full dark lines at the start of every frame. und er normal circumstances, these pixels do not respond to light and may be used as a dark reference. surrounding each dark reference region are two columns (or rows) that are also light shielded pixels. these columns (or rows) may have some light leakage eff ects from surrounding pixels and therefore, should not be used as a dark reference. the regions labeled gray are a combination of light shielded pixels and light sensitive pixels. these pixels should not be used as a dark reference. for every 5 columns in the gray region 4 columns are covered by lightshield and 1 column is open. these open columns are covered with blue color filter. eight buffer pixels contain a rgb mosaic color pattern. this region is classified as active buffer pixels. these pixels are l ight sensitive but they are not tested for defects and non - uniformities. the response of these pixels will not be uniform. vouta color fill pattern 1880 active pixel s/li ne (typical active li ne format) gr r b r r b gr r gr r gr r gb r active image area 3760 (h) x 2840 (v) kai-10100 3776 (h) x 2856 (v) 4:3 aspect ratio 4.75 microns x 4.75 microns pixels effective image area 4 4 1 2 37 6 4 8 a c t i v e b u f f e r c o l u m n s 8 a c t i v e b u f f e r c o l u m n s 7 4 d a r k r e f e r e n c e c o l u m n s 4 d a r k d u m m y c o l u m n s 2 dark dummy rows 20 dark reference rows 4 gray rows 2 dark dummy rows 4 gray rows 2 d a r k d u m m y c o l u m n s 2 8 4 0 a c t i v e l i n e s / f r a m e voutb 1880 active pixel s/li ne (typical active li ne format) 4 4 1 2 37 6 4 3760 active col umns/frame (r, gbr) (grr, b) d u m m y c o l u m n s d a r k d u m m y c o l u m n s a c t i v e b u f f e r c o l u m n s a c t i v e b u f f e r c o l u m n s d a r k d u m m y c o l u m n s d a r k r e f e r e n c e c o l u m n s d a r k d u m m y c o l u m n s functionality not defined in the region as marked: 8 active buffer rows 8 acti ve buffer rows 4 gray rows 1 2 d a r k d u m m y c o l u m n s
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 8 pixel an electronic representation of an image is formed when incident photons falling on the sensor plane create electron - hole pai rs within the individual silicon photodiodes. these photoelectrons are collected locally by the formation of potential wells at each photosite. below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon lig ht level and exposure time and non - linearly dependent on wavelength. when the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. vertical to horizontal transfer when the vx timing inputs are pul sed, charge in every pixel of the vccd is shifted one row towards the hccd. when the vccd is shifted, the timing signals to the hccd must be stopped and htg input must be high. h2 must be stopped in the high state while h1, h3, h4 and h4l must be stopped in the low state. the hccd clocking may begin 15.6 ns after the falling edge of the htg. charge is transferred from the last v1 phase of the even column vccd into hccda, while the charge from the last v1 phase of the odd columns is transferred into hccdb . horizontal register to floating diffusion there are 2 hccds, each has a total of 1938 pixels. the even vertical shift registers (columns) are shifted into hccda and the odd vertical shift registers are shifted into hccdb. at the beginning of each hccd register there are 4 dummy pixels, these pixels receive no charge from the vertical shift registers. the first 4 clock cycles of the hccd will be empty pixels (containing no electrons). the next 2 clock cycles will contain only electrons generated by dark current in the vccd and photodiodes. the next 4 clock cycles will contain active buffer column signal. the image data is found in the next 1880 clock cycles which contain photo - electrons. following the image data there will be another 4 buffer columns and 1 dark dummy column. finally, there are 37 dark reference columns followed by the 6 more dark dummy columns. when the hccd is shifting valid image data, the timing inputs to the electronic shutter (sub), vccd (vx), and htg should be not be pulsed. this p revents unwanted noise from being introduced
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 9 h orizontal r egister output structure figure 2 : output architecture (each output) charge packets contained in the horizontal register are dumped pixel by pixel onto the floating diffusion (fd) output node whose potential varies linearly with the quantity of charge in each packet. the amount of potential charge is determined by the expre ssion vfd= q/cfd. a three - stage source - follower amplifier is used to buffer this signal voltage off chip with slightly less than unity gain. the translation from the charge domain to the voltage domain is quantified by the output sensitivity or charge to voltage conversion in terms of microvolts per electron ( v/e - ). the dual parallel horizontal ccds are presented a new line during the horizontal retrace period. h1, h3, h4 and h4l are held low while the vertical registers transfer the next line to the hori zontal. h2 and htg are held high. htg shifts low then h1 taken high. this shifts the charge in the horizontal registers forward one phase so the charge packets in the a and b registers are now aligned. both horizontal ccds then transport each line, pixel by pixel, to the a and b output structures by clocking the h1 and h2 pins alternately with the h3 and h4 pins in a complementary fashion. a separate connection to the last h4 phase (h4l) is provided to improve the transfer speed of charge to the floating diffusion. on each falling edge of h4l a new charge packet is dumped onto a floating diffusion and sensed by the output amplifier. after the signal has been sampled off chip, the reset clock (rg) removes the charge from the floating diffusion and resets it s potential to the reset drain voltage (rd), which is set on - chip. internal connections esd rf3 rf4 rf2 rf1 rg (reset) rd rden floating diffusion vout vdd sub sub15 16k 4k 1.5k 1.5k 0.75k 18k 7.5k 10k 100k
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 10 r ecommended c ircuits output gate bypass figure 3 : cog circuit output load figure 4 : recommended output structure load diagram. component values may be revised based on operating conditions and other design considerations . cog pin 6 c cog 0.1uf 2n3904 or equiv. 140 ohms buffered video output iout = 5 ma vdd = +15 v 1k ohms 0.1 f vout
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 11 p hysical d escription pin description and device orientation figure 5 : pinout diagram pin name description pin name description 1 vouta video output a 32 sub15 sub voltage reference supply 2 rg reset gate 31 subs sub voltage reference still 3 gnd ground 30 subv sub voltage reference video 4 voutb video output b 29 v2 - 10 vccd gates 2 and 10 5 vdd amplifier supply 28 v4 - 12 vccd gates 4 and 12 6 cog og bypass capacitor 27 v1 vccd gate 1 7 h4l last hccd gate, same as h4 26 v9 vccd gate 9 8 esd esd circuit disable input 25 v5 vccd gate 5 9 gnd ground 24 v13 vccd gate 13 10 sub sensor substrate clock input 23 sub sensor substrate clock input 11 gnd ground 22 v3 vccd gate 3 12 htg hccd transfer gate 21 v11 vccd gate 11 13 h4 hccd gate 4 20 v7 vccd gate 7 14 h3 hccd gate 3 19 v15 vccd gate 15 15 h2 hccd gate 2 18 v6 - 14 vccd gates 6 and 14 16 h1 hccd gate 1 17 v8 - 16 vccd gates 8 and 16
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 12 imaging performance t ypical o perational c onditions description condition - unless otherwise noted notes integration time (33msec) + field readout time (treadout ) 93 msec C field 1 153 msec C field 2 213 msec C field 3 273 msec C field 4 integration time (tint) 33 msec specified between the end of the electrical shutter pulse and the flush. horizontal clock frequency 30 mhz light source (led) red green blue orange mode e electronic shutter C integrate C flush C f1 transfer read, f2 transfer read, readout cycles temperature 20 c (except where noted) s pecifications (fa mode, unless specified) kai - 10100 - cxb color with microlens description symbol min. nom. max. units specified temperature notes sample plan 7 maximum photoresponse nonlinearity nl n/a 8 % 1, 2 design maximum gain difference between outputs g n/a 2 % 1, 2 design max. signal error due to nonlinearity dif. nl n/a 3 % 1, 2 design horizontal ccd charge capacity hne 70 ke - design vertical ccd charge capacity vne tbd 50 ke - die photodiode charge capacity pne 22.5 25 ke - die horizontal ccd charge transfer efficiency hcte 0.99999 n/a design vertical ccd charge transfer efficiency vcte 0.99999 n/a design photodiode dark current ipd n/a 3 50 e/p/s 40 die photodiode dark current ipd n/a .06 na/cm 2 40 die vertical ccd dark current ivd n/a 115 450 e/p/s 40 die image lag lag n/a 5 e - design blooming suppression xab 100 design vertical smear smr n/a - 85 - 75 db 6 design total noise n e - t 10 e - rms 3 design dynamic range dr 64 db 4 design output amplifier dc offset v odc 6.5 7.5 9.3 v die output amplifier bandwidth f - 3db 88 140 176 mhz 5 die output amplifier impedance r out 100 160 200 ohms die output amplifier sensitivity v/ n 32 v/e - design peak red q uantum green ef f iciency blue qe max 32 42 40 n/a n/a n/a % design peak quantum red efficiency wavelength green blue qe max 630 550 470 n/a n/a n/a nm design
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 13 notes: 1. value is over the range of 10% to 90% of photodiode saturation. 2. value is for the sensor operated without binning . 3. includes system electronics noise, dark pattern noise and dark current shot noise at 30 mhz. 4. uses 20log(pne/ n e - t ) . 5. last stage only, c load =10 pf. then f - 3db = (1 / (2 *r out *c load )) . 6. fb2 timing mode (1 x 2 binning) . 7. die indicates a parameter that is measured on every sensor during the production testing. design designates a par ameter that is quantified during the design verification activity.
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 14 typical performance curves figure 6 : typical spectral response C clear cover glass figure 7 : typical angular response C clear cover glass kai - 10100 - cxb spectral response 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 350 400 450 500 550 600 650 700 750 wavelength (nm) absolute qe r b gr gb 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 -25 -20 -15 -10 -5 0 5 10 15 20 25 angle normalized response horizontal - white light vertical - white light
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 15 figure 8 : power vs. clock rate 0 100 200 300 400 500 600 10 12 14 16 18 20 22 24 26 28 30 power (mw) hccd frequency (mhz) power vs ccd clock frequency full resolution fa mode 1x2 binning fb2 mode 2x2 binning fb4 mode 4x4 binning fd16 mode
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 16 defect definitions o perational c onditions all defect tests performed using the following conditions: description condition - unless otherwise noted notes temperature 20 c integration time (tint) 33 msec timing mode fa s pecifications description definition standard grade notes sample plan major dark field defective pixel defect 200 mv 2000 1 die major bright field defective pixel defect 15 % 1 die minor dark field defective pixel defect 30 mv 2000 1 die cluster defect a group of 2 to n contiguous major defective pixels 20 n=20 1 die column defect a group of more than 20 contiguous major defective pixels along a single column 40 1 die notes: 1. tested at 20 c.
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 17 test definitions t est r egions of i nterest active area roi: pixel ( 1, 1 ) to pixel ( 3760, 2840 ) center 210 by 210 roi: pixel ( 1775, 1315 ) to pixel ( 1985, 1525 ) only the active pixels are used for performance and defect tests. o ver c locking the test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. see figure 9 for a pictorial representation of the regions. figure 9 : overclock regions of interest
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 18 t ests dark field defect test this test is performed under dark field condi tions. the sensor is partitioned into 252 sub regions of interest, each of which is 210 by 210 pixels in size. in each region of interest, the median value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater th an or equal to the median value of that region of interest plus the defect threshold specified in the defect definitions section. bright field defect test this test is performed with the imager illuminated to a level such that the output is at approximat ely green: 700 mv (22,000 e - ), red & blue: 450 mv (14,000 e - ). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 28,000 electrons (900 mv). the average signal level of all active pixels is found. the bright and dark thresholds are set as: dark defect threshold = active area signal * threshold bright defect threshold = active area signal * threshold dark defect threshold = 200 mv (major defects); 30 mv (minor defects) bright defect threshol d = any pixel that deviates more than 15% of average of su rrounding pixels in a 210 x 210 roi average green = 700 mv upper = 805 mv lower = 695 mv average red & blue = 450 mv upper = 517.5 mv lower = 382.5 mv the sensor is then partitioned into 252 sub regions of interest, each of which is 210 by 210 pixels in size. in each region of interest, the average value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. example for major bright field defective pixels: ? average value of all active pixels is found to be 700 mv (22,000 electrons). ? dark defect threshold: 700mv * 15% = 105 mv (limit 695 mv to 805 mv) . ? bright defect threshold: 200mv * 15% = mv . ? region of interest #1 selected. this region of interest is pixels 1, 1 to pixels 210, 210. o m edian of th is region of interest is found to be 700 mv. o any pixel in this region of interest that is (700+105 mv) 805 mv in intensity will be marked defective. o any pixel in this region of interest that is (700 - 105 mv) 695 mv in intensity will be marked defective. ? all remaining 251 sub regions of interest are analyzed for defective pixels in the same manner.
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 19 operation a bsolute m aximum r atings device pin minimum maximum units notes vdd, vout, sub15, subs, subv - 0.4 17.5 v v1, v3, v5, v7, v9, v11, v13, v15 vesd - 0.4 vesd +24 v v2_10, v4_12, v6_14, v8_16 vesd - 0.4 vesd +14 v h1, h2, h3, h4, h4l, htg, rg, cog vesd - 0.4 vesd +14 v esd - 10 0 v sub - 0.4 47.4 v 1 notes: 1. refer to application note using interline ccd image sensors in high intensity visible lighting conditions .
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 20 p ower - up s equence figure 10 : power - up sequence diagram power up esd, sub, and sub15 in any order first. once the esd voltage is stable and sub is above 3 v all other biases can be turned on in any order. subv and subs should only drive high impedance circuitry. the image sensor can be protected from an accidental improper esd voltage setting by current limiting the sub voltage to less tha n 10 ma (that is the 4.7k resistor). do not pulse the electronic shutter until esd is stable. sub, sub15, and vdd mu st always be greater than gnd. esd must always be less than gnd. placing diodes between sub, sub15, vdd and esd pins and gnd will protect th e sensor from accidental overshoot of vdd, sub and esd during power - on or power - off. the vccd clock waveform must not have a negative overshoot more than 0.5 v below the esd voltage. figure 11 : diagram of vertical clock overshoo t to be avoided a lternate p ower u p s equence if vdd is to be powered up at the same time as sub15 and sub then vdd must be less than 10 v until sub is greater than 3 v. *** vdd cannot be +15 v when sub is 0v *** 0 v+ v - sub15 sub esd vccd low hccd low vdd all vccd clocks absolute maximum overshoot of 0.5 v esd esd - 0.5 v 0 v
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 21 dc b ias o perating c onditions description symbol minimum nominal maximum units maximum dc current (ma) notes output amplifier supply vdd 14.5 15.0 15.5 v substrate, supply sub15 14.65 15.0 15.35 v substrate, input sub - 0.1 subs, subv,15v nominal + es v <200 ma 4, 5, 7 output gate cog n/a, not supplied by user 3 video output current iout - 5 ma 1 vnl - vesd difference - 0.2 0 0.2 2, 6 reset gate rg - 0.2 0 0.2 2 notes: 1. an output load sink must be applied to vout to activate output amplifier. see figure 8 . 2. vesd should tie directly to vertical low (vl) clock driver bias level. 3. voltage is set by image sensor and will be between gnd and C 4 v. connect to ground via a bypass capacitor with recommended value as shown. 4. peak ac current will be much higher due to the 4.3nf load of the substrate. substrate input level (1 of 4) is set to support the timing mode; (fa = subs, fbx = subv, fd16 = 15v). 5. es is the electrical shutter voltage. see ac operating conditions, clock levels, for the definition. 6. suffix n refers to all vertical clock pins; v2 - 10, v4 - 12, v1, v9, v5, v13, v3, v11, v7, v15, v6 - 14, v8 - 16. for any vertical clock, the low level cannot ex ceed these values. 7. refer to application note using interline ccd image sensors in high intensity visible lighting conditions . s upplied v oltage l evels description symbol minimum nominal maximum units maximum dc current (ma) notes substrate, outputs subv, subs 7.45 10.47 13.39 v 1 note: 1. voltage level defined by individual device on - chip circuitry.
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 22 ac o perating c onditions clock levels description symbol level minimum nominal maximum units notes vertical clock low level vnl low - 9.0 - 8.75 - 8.5 v 1,3 vertical clock mid - level vnm mid - 0.1 0.0 0.1 v 1,3 vertical clock high level vnh high 12.75 13 13.25 v 1,3 horizontal clock low level hl low - 4.3 - 4.1 - 3.9 v 1 horizontal clock high level hh high - 0.1 0.0 1 v 1 electronic shutter pulse amplitude es 30 32 34 v 1,2,4 rg amplitude rga - 3.1 3.3 4.3 v htg high hth high 3.9 4.1 4.3 v 1 htg low htl low - 4.7 - 4.1 - 4.3 v notes: 1. all pins draw less than 10ma dc current. capacitance values relative to sub (substrate). 2. the electronic shutter level is referenced to sub (typically). 3. suffix n refers to all vertical clock pins; v2 - 10, v4 - 12, v1, v9, v5, v13, v3, v11, v7, v15, v6 - 14, v8 - 16 4. refer to application note using interline ccd image sensors in high intensity visibl e lighting conditions . clock capacitance clock capacitance units v1 6.5 nf v3 6.5 nf v5 6.5 nf v7 6.5 nf v9 6.5 nf v11 6.5 nf v13 6.5 nf v15 6.5 nf v2_v10 13 nf v4_v12 13 nf v6_v14 13 nf v8_v16 13 nf h1 85 pf h2 85 pf h3 85 pf h4 85 pf htg 30 pf h4l 10 pf reset 10 pf sub 4.3 nf
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 23 timing r equirements and c haracteristics description symbol minimum nominal maximum units notes hccd clock period t h 33 - - ns hccd delay t hd - 15.6 - ns 1 htg pulse time t htg - 8 - s 2 vccd transfer time t vccd - 2.0 - s 3 vccd pedestal time t 3p - 2 - s 4 photodiode transfer time t v3rd 5.0 6 - s 4 vccd delay t 3d - 4 - s 4 reset pulse time t r - 2.0 - ns shutter pulse time t s - 7 - s 5 shutter pulse delay t sd - 15.6 - vertical clock edge alignment t ve 0.0 - 100 ns vodd rise time t v1r 0.5 0.75 1.0 us veven rise time t v2r 0.5 0.75 1.0 us vodd fall time t v1f 0.5 0.75 1.0 us veven fall time t v2f 0.5 0.75 1.0 us vodd pulse width t v1w 2.0 - - us veven pulse width t v2w 2.0 - - us h1, h2 rise time t h1r - - 4 ns h3, h4 rise time t h2r - - 4 ns h1, h2 fall time t h1f - - 4 ns h3, h4 fall time t h2f - - 4 ns h1, h2 rise time, ff mode t h1r - - 6 ns h3, h4 rise time, ff mode t h2r - - 6 ns h1, h2 fall time, ff mode t h1f - - 6 ns h3, h4 fall time, ff mode t h2f - - 6 ns htg, h1 alignment rise time t ht,1r 0 ns htg, h1 alignment fall time t ht,1f 13 ns h1, h2 C h3, h4 pulse width t h1w , t h3w 16.5 ns h4l rise time t h1lr 2 ns h4l fall time t h1lf 2 ns h4l pulse width t h1lw 16.5 ns rg rise time t rgr - 2 ns rg fall time t rgf - 2 ns rg pulse width t rgw - 2 - ns es pulse width t esw - 20 ns notes: 1. last hclk to htg rise. 2. see timing sequence ve. 3. vccd to hccd transfer pulse, see timing sequence ve, vg, vn. 4. photodiode to vccd transfer sequence see sequence va, vb, vc, vd, vf . 5. electronic shutter timing see timing sequence vg .
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 24 timing modes timing mode sensor output binning 30 mhz fps vertical notes x y megapixel x y sequences pixel purpose fa 3760 28 40 10.68 1 1 4.67 va, vb, vc, vd, ve 4.75 x 4.75 full resolution 4 field interlaced 1 fb2 3760 1420 5.34 1 2 10.07 vf, vg 4.75 x 9.5 progressive scan 2 fb4 1880 1420 2.67 2 2 10.07 vf, vn 9.5 x 9.5 progressive scan 2 fd16 940 710 .67 4 4 19.01 vh, vi 19 x 19 progressive scan 3 notes: 1. substrate input level for fa mode = subs. nominal linear photodiode capacity 22.5 ke - . 2. substrate input level for fbx mode = subv. nominal linear photodiode capacity 20.0 ke - . 3. substrate input level for fd16 mode = 15v. nominal linear photodiode capacity 10 ke - . figure 12 : frame rates 0 5 10 15 20 25 30 10 14 18 22 26 30 frames per second hccd frequency (mhz) full resolution fa mode 1x2 binning fb2 mode 2x2 binning fb4 mode 4x4 binning fd16 mode
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 25 f ull r esolution i nterlaced r eadout (fa m ode ) flow chart fa this is the 10 mp full resolution mode. the image is read out four field interlaced. figure 13 : fa mode - timing flow electronic shutter clears photodiodes mechanical shutter opens timing sequence ve clears vccd of smear repeat 800 times timing sequence va photodiode to vccd transfer of field 1 timing sequence ve repeat 723 times timing sequence vb photodiode to vccd transfer of field 2 timing sequence ve image capture finished clock hccd for 1938 cycles repeat 723 times clock hccd for 1938 cycles timing sequence vc photodiode to vccd transfer of field 3 timing sequence ve repeat 723 times clock hccd for 1938 cycles timing sequence vd photodiode to vccd transfer of field 4 timing sequence ve repeat 723 times clock hccd for 1938 cycles set all vccd clocks to the vl voltage. do not clock vccd. mechanical shutter closes 34 33 36 35 38 37 40 39 field 2 (vb) field 1 (va) field 4 (vd) field 3 (vc) field 2 (vb) field 1 (va) field 4 (vd) field 3 (vc) row
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 26 fa mode pixel order field rows vertical sequence hccd a color hccd b color 1 2, 6, 10 ... va green blue 2 1, 5, 9 ... vb red green 3 4, 8, 12 ... vc green blue 4 3, 7, 11 ... vd red green figure 14 : fa mode C pixel order diagram
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 27 f a frame rate total time for mechanical shutter to open and close n umber of lines to flush vccd after shutter closes (800) n umber of lines to read out of the image sensor (2892) n umber of clock cycles in one line (1938) vccd transfer time (1.0 s) h ccd clock frequency (mhz) = t otal time of sequences va+vb+vc+vd = 80 s ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? f n t n n t t t t t c vccd l f ms vd vc vb va ) 2 ( 8 10 6 ? ms t ? f n ? l n ? c n ? vccd t ? f vd vc vb va t t t t ? ? ?
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 28 fa clocking overview figure 15 : fa timing over view field 4 field 3 frame line v15 v13 v11 v9 v8 - 16 v7 v6 - 14 v5 v4 - 12 v3 v2 - 10 line 0 line 4 line 8 line 2884 line 2888 line 1 line 5 line 9 line 2885 line 2889 line 2 line 6 line 10 line 2886 line 2890 line 3 line 7 line 11 line 2887 line 2891 line 0 v1 h clocks field 1 field 2 new frame a b c d e f transfer charge from pd to vccd transfer charge from pd to vccd t ransfer charge from pd to vccd transfer charge from pd to vccd transfer charge from pd to vccd transfer charge from pd to vccd transfer charge from pd to vccd transfer charge from pd to vccd see enlarge a,b,c,d,e,f transfer charge from pd to vccd transfer charge from pd to vccd
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 29 figure 16 : fa integration timing overview
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 30 p rogressive s can 1 x 2 b inning r eadout (fb2 m ode ) flow chart fb2 this is the ? resolution mode. the image is read out progressive scan. the primary use of this mode is for low light photography at higher frame rate. figure 17 : f b2 mode - timing flow vertical sequence vf transfers all photodiodes to vccd repeat for 1446-n lines vertical sequence vg clock hccd for 1938 cycles pulse electronic shutter on vsub repeat for n lines exposure time = n lines vertical sequence vg clock hccd for 1938 cycles 34 33 36 35 38 37 40 39 row vccd binning (vf)
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 31 p rogressive s can 2 x 2 b inning r eadout (fb4 m ode ) flow chart fb4 this is the ? resolution mode. four pixels are summed together. the image is read out progressive scan. primary use of this mode is for low light photography at higher frame rate. figure 18 : f b4 mode - timing flow vertical sequence vf transfers all photodiodes to vccd repeat for 1446-n lines vertical sequence vn clock hccd for 1938 cycles pulse electronic shutter on vsub repeat for n lines exposure time = n lines vertical sequence vn clock hccd for 1938 cycles 34 33 36 35 38 37 40 39 row vccd binning (vf) 9 10 11 12 column 5 6 7 8 column hccd binning (vn) 5 6 7 8 9 10 11 12
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 32 p rogressive s can 4 x 4 b inning r eadout (fd16 m ode ) flow chart fd16 this is a full image preview mode for low light levels. all pixels are sampled. four pixels are summed in the vccd and four pixels are summed on the output amplifier floating diffusion. figure 19 : f d16 mode - timing flow vertical sequence vh transfers all photodiodes to vccd repeat for 723-n lines vertical sequence vi clock hccd for 1938 cycles pulse electronic shutter on vsub repeat for n lines exposure time = n lines vertical sequence vi clock hccd for 1938 cycles 42 41 44 43 46 45 48 47 9 10 11 12 5 6 7 8 34 33 36 35 38 37 40 39 row 9 10 11 12 column 5 6 7 8 vccd 4x bin (vh) 17 18 19 20 13 14 15 16 column hccd 4x bin (vi)
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 33 there is a missing clock cycle on h2 of timing sequence vi. this unusual timing at the beginning of each line provides a more evenly spaced bayer color pattern. with the missing clock cycles output a is the sum of columns 12+14+16+18 and output b is the sum of columns 9+11+13+15. if there were no missing clock cycle then output a would be the sum of columns 10+12+14+16 and output b would be the sum of columns 9+11+13+15. figure 20 : f d16 mode C clock order information 9 10 11 12 13 14 15 16 17 18 19 20 + + + + 21 22 23 24 25 26 column number 9 10 11 12 13 14 15 16 17 18 19 20 + + + + 21 22 23 24 25 26 column number better spacing of summed pixels when there is a missing clock cycle at the beginning of each line of h2 poor spacing of summed pixels when there is no missing clock cycle at the beginning of each line of h2
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 34 vertic al timing sequence fa m ode sequence va transfers field 1 from the photodiodes to vccd. this is for full resolution readout. no vccd binning. 8 phase vccd. figure 21 : fa mode C vertical timing sequence - va v1 v3 v4_12 v5 v6_14 v7 v9 v11 v13 v15 2 4 6 8 v2_10 v8_16 0 vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vh vm vl vh vm vl vh time (s) vccd clock signal vccd clock voltage
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 35 sequence vb transfers field 2 from the photodiodes to vccd. this is for full resolution readout. no vccd binning. 8 - phase vccd. figure 22 : fa mode C vertical timing sequence - vb v1 v3 v4_12 v5 v6_14 v7 v9 v11 v13 v15 2 4 6 8 10 12 14 16 18 20 22 24 v2_10 v8_16 0 vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vh vm vl vh vm vl vh time (s) vccd clock signal vccd clock voltage
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 36 sequence vc transfers field 3 from the photodiodes to vccd. this is for full resolution readout. no vccd binning. 8 - phase vccd. figure 23 : fa mode C vertical timing sequence - vc v1 v3 v4_12 v5 v6_14 v7 v9 v11 v13 v15 2 4 6 8 10 12 14 16 18 20 22 24 v2_10 v8_16 0 vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vh vm vl vh vm vl vh time (s) vccd clock signal vccd clock voltage
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 37 sequence vd transfers field 4 from the photodiodes to vccd. this is for full resolution readout. no vccd binning. 8 - phase vccd. figure 24 : f a mode C vertical timing sequence - vd v1 v3 v4_12 v5 v6_14 v7 v9 v11 v13 v15 2 4 6 8 10 12 14 16 18 20 22 24 v2_10 v8_16 0 vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vh vm vl vh vm vl vh time (s) vccd clock signal vccd clock voltage
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 38 sequence ve transfers one row from the vccd into the hccd. this is for full horizontal resolution readout. no hccd binning. 8 - phase vccd. figure 25 : fa mode C vertical timing sequence - ve h3 h1 h2 h4 and h4l htg reset video each clock cycle is 15.6 ns v1 and v9 v2_10 v3 and v11 v4_12 v5 and v13 v6_14 v7 and v15 v8_16 1 5 . 6 n s 1.0 s each vm vl hh hl hh hl hh hl hh hl vm vl vm vl vm vl vm vl vm vl vm vl vm vl 1 5 . 6 n s output a = column 6 output b = column 5 output a = column 8 output b = column 7 reset runs continuously 1 2 3 4 5 6 7 8 9 10 11 1 1938 1937 1936 1935 pixel count hth htl
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 39 fb2 and fb4 m ode sequence vf this sums together two rows in the vccd. progressive scan readout. vertical resolution is reduced by a factor of 2. 4 - phase vccd. figure 26 : f b2/fb4 mode C vertical timing sequence - vf v1, v9 v3, v11 v4_12, v8_16 v5, v13 v7, v15 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 v2_10, v6_14 0 vccd clock signal vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vh time (s) vccd clock voltage
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 40 sequence vg this transfers one row from the vccd to the hccd. there is no horizontal binning. 4 - phase vccd. figure 27 : f b2/fb4 mode C vertical timing sequence - vg h3 h1 h2 h4 and h4l htg reset video each clock cycle is 15.6 ns 1 5 . 6 n s 1.0 s each hh hl hh hl hh hl hh hl vm vl 1 5 . 6 n s output a = column 6 output b = column 5 output a = column 8 output b = column 7 reset runs continuously v1, v5, v9, v13 v2_10, v6_14 v3, v7, v11, v15 v4_12, v8_16 vm vl vm vl vm vl 1 2 3 4 5 6 7 8 9 10 11 1 1938 1937 1936 1935 pixel count 7 s 5 s vsub hth htl
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 41 sequence vn transfers one row from the vccd to the hccd. two charge packets are summed together on the amplifier floating diffusion. 4 - phase vccd. figure 28 : f b2/fb4 mode C vertical timing sequence - vn h3 h1 h2 h4 and h4l htg reset video each clock cycle is 15.6 ns 1 5 . 6 n s 1.0 s each hm hl hm hl hm hl hm hl vm vl 1 5 . 6 n s output a = column 6+8 output b = column 5+7 output a = column 10+12 output b = column 9+11 reset runs continuously v1, v5, v9, v13 v2_10, v6_14 v3, v7, v11, v15 v4_12, v8_16 vm vl vm vl vm vl hth htl
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 42 fd16 m ode sequence vh this sums together 4 rows in the vccd. progressive scan readout. vertical resolution is reduced by a factor of 4. 8 - phase vccd. figure 29 : fd16 mode C vertical timing sequence - vh v1 v3 v4_12 v5 v6_14 v7 v9 v11 v13 v15 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 v2_10 v8_16 0 64 vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vm vl vh vm vl vh vm vl vh vm vl vh time (s) vccd clock signal vccd clock voltage
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 43 sequence vi transfers one row from the vccd to the hccd. sums together 4 charge packets on the amplifier floating diffusion. 8 - phase vccd. figure 30 : fd16 mode C vertica l timing sequence - vi h3 h1 h2 h4 and h4l htg reset runs continuously output a = sum of columns 4+6+8+10 output b = sum of columns 1+3+5+7 each clock cycle is 15.6 ns v1 and v9 v2_10 v3 and v11 v4_12 v5 and v13 v6_14 v7 and v15 v8_16 1 5 . 6 n s 1.0 s each vm vl hh hl hh hl hh hl hh hl vm vl vm vl vm vl vm vl vm vl vm vl vm vl 1 5 . 6 n s reset video hth htl
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 44 e lectronic s huttering the voltage on the substrate (sub) determines the charge capacity of the photodiodes. when sub is at vsubs volts the photodiodes will be at their maximum charge capacity. increasing vsub above vsubs volts decre ases the charge capacity of the photodiodes until 30 volts when the photodiodes have a charge capacity of zero electrons. therefore, a short pulse on sub, with a peak amplitude greater than 30 volts, empties all photodiodes and provides the electronic shut tering action. it may appear the optimal substrate voltage setting is vsubs volts to obtain the maximum charge capacity and dynamic range. while setting vsub to vsubs volts will provide the maximum dynamic range, it will also provide the minimum antibloomi ng protection. the kai - 10100 vccd has a nominal linear charge capacity of 50,000 electrons (50.0 ke - ). if the sub voltage is set such that the photodiode holds more than 50 ke - , then when the charge is transferred from a full photodiode to vccd, the vccd will overflow. this overflow condition manifests itself in the image by making bright spots appear elongated in the vertical direction. the size increase of a bright spot is called blooming when the spot doubles in size. the blooming can be eliminated by increasing the voltage on sub to lower the charge capacity of the photodiode. this ensures the vccd charge capacity is greater than the photodiode capacity. there are cases where an extremely bright spot will still cause blooming in the vccd. normally, whe n the photodiode is full, any additional electrons generated by photons will spill out of the photodiode. the excess electrons are drained harmlessly out to the substrate. there is a maximum rate at which the electrons can be drained to the substrate. if t hat maximum rate is exceeded, (for example, by a very bright light source) then it is possible for the total amount of charge in the photodiode to exceed the vccd capacity. this results in blooming. the amount of antiblooming protection also decreases wh en the integration time is decreased. there is a compromise between photodiode dynamic range (controlled by vsub) and the amount of antiblooming protection. a low vsub voltage provides the maximum dynamic range and minimum (or no) antiblooming protection. a high vsub voltage provides lower dynamic range and maximum antiblooming protection. the kai - 10100 has internal circuitry that will output the optimal setting of vsub for fa and fbx modes. this voltage should be buffered and fed back to the vsub of the de vice. for fd mode the vsub should be set to 15 v. the electronic shutter provides a method of precisely controlling the image exposure time in fb2, fb4 and fd16 modes without any mechanical components. if an integration time of tint is desired, then the s ubstrate voltage of the sensor is pulsed to at least 30 volts tint seconds before the photodiode to vccd transfer pulse on vx. the electronic shutter pulse on vsub can only be pulsed when the hccd does not contain valid image charge. the shutter pulse wil l empty the hccd of charge. the best place for the electronic shutter pulse is at the end of a line when the hccd is empty and before the vccd transfers another line into the hccd. ideally, the electronic shutter pulse would occur once for each image rea d out. only one line of the image would be extended by 0.7 s to insert the electronic shutter pulse. this minimizes the power requirements and time to read out an image.
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 45 storage and handling s torage c onditions description symbol minimum maximum units notes storage temperature t st - 20 80 c 1 humidity rh 5 90 % 2 notes: 1. long - term exposure toward the maximum temperature will accelerate color filter degradation. 2. t=25 c. excessive humidity will degrade mttf. esd 1. this device contains limited protection against electrostatic discharge (esd). esd events may cause irreparable damage to a ccd image sensor either immediately or well after the esd event occurred. failure to protect the sensor from electrostatic discharge may affect device performance and reliability. 2. devices should be handled in accordance with strict esd procedures for class 0 (<250v per jesd22 human body model test), or class a (<200v jesd22 machine model test) devices. devices are shipped in static - sa fe containers and should only be handled at static - safe workstations. 3. see application note image sensor handling best practices for proper handling and grounding procedures. this application note also contains workplace recommendations to minimize electro static discharge. 4. store devices in containers made of electro - conductive materials. c over g lass c are and c leanliness 1. the cover glass is highly susceptible to particles and other contamination. perform all assembly operations in a clean environment. 2. tou ching the cover glass must be avoided. 3. improper cleaning of the cover glass may damage these devices. refer to application note image sensor handling best practices . e nvironmental e xposure 1. extremely bright light can potentially harm ccd image sensors. do not expose to strong sun light for long periods of time, as the color filters and/or microlenses may become discolored. in addition, long time exposures to a static high contrast scene should be avoided. localized changes in response may occur from color f ilter/microlens aging. for interline devices, r efer to application note us ing interline ccd image sensors in high intensity visible lighting conditions . 2. exposure to temperatures exceeding maximum specified levels should be avoided for storage and operation , as device performance and reliability may be affected. 3. avoid sudden temperature changes. 4. exposure to excessive humidity may affect device characteristics and may alter device performance and reliability, and therefore should be avoided. 5. avoid storage of the product in the presence of dust or corrosive agents or gases, as deterioration of lead solderability may occur. it is advised that the solderability of the device leads be assessed after an extended period of storage, over one year. s oldering r ecomm endations 1. the soldering iron tip temperature is not to exceed 370 c. higher temperatures may alter device performance and reliability. 2. flow soldering method is not recommended. solder dipping can cause damage to the glass and harm the imaging capability of the device. recommended method is by partial heating using a grounded 30 w soldering iron. heat each pin for less than 2 seconds duration.
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 46 mechanical drawings c ompleted a ssembly figure 31 : completed assembly (1 of 2)
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 47 figure 32 : completed assembly (2 of 2)
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 48 c over g lass figure 33 : glass drawing
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 49 figure 34 : glass transmission 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 300 350 400 450 500 550 600 650 700 750 800 850 900 wavelength (nm ) transmission (%)
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 50 quality assurance and reliability q uality and r eliability all image sensors conform to the specifications stated in this document. this is accomplished through a combination of statistical process control and visual inspection and electrical testing at key points of the manufacturing proces s, using industry standard methods. information concerning the quality assurance and reliability testing procedures and results are available from on semiconductor upon request. for further information refer to applicatio n note quality and reliability . r ep lacement all devices are warranted against failure in accordance with the terms of sale . devices that fail due to mechanical and electrical damage caused by the customer will not be replaced. l iability of the s upplier a reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the customer. product liability is limited to the cost of the defective item, as defined in the terms of sale . l iability of the c ustomer damage from mishandling (scratches or breakage), electrostatic discharge (esd), or other electrical misuse of the device beyond the stated operating or storage limits, which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer. t est d ata r etention image sensors shall have an identifying number traceable to a test data file. test data shall be kept for a period of 2 years after date of delivery. m echanical the device assembly drawing is provided as a reference. on semiconductor reserves the right to change any information c ontained herein without notice. all information furnished by on semiconductor is believed to be accurate. life support applications policy on semiconductor image sensors are not authorized for and should not be used within life support systems without the specific written consent of on semiconductor .
ka i - 10100 image sensor www.truese nseimaging.com revision 1.1 ps - 0027 pg 51 ? 2014, semiconductor components industries, llc. revision changes mtd/ps - 1029 revision number description of changes 1.0 ? initial release. 2.0 ? added catalog numb ers 4h2106 and 4h2107 3.0 ? added the note refer to application note using interline ccd image sensors in high intensity visible lighting conditions to the following sections o absolute maximum ratings o dc bias operating conditions o ac operating conditions o storage and handling ? changed cover glass material to d263t eco or equivalent ps - 00 27 revision number description of changes 1.0 ? initial release with new document number, updated branding and document template ? updated storage and handling and quality assurance and reliability sections 1.1 ? updated branding

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